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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6708A/D
64K x 4 Bit Static RAM
The MCM6708A is a 262,144 bit static random access memory organized as 65,536 words of 4 bits, fabricated using high-performance silicon-gate BiCMOS technology. Static design eliminates the need for external clocks or timing strobes. The MCM6708A is available in a 300 mil, 24 lead plastic surface-mount SOJ package. * * * * * Single 5 V 10% Power Supply Fully Static -- No Clock or Timing Strobes Necessary All Inputs and Outputs are TTL Compatible Three State Outputs Fast Access Times: MCM6708A-8 = 8 ns MCM6708A-10 = 10 ns MCM6708A-12 = 12 ns
MCM6708A
J PACKAGE 300 MIL SOJ CASE 810A-02
PIN ASSIGNMENT
1 2 3 4 5 6 7 8 9 10 11 12 VCC A15 A14 A13 A12 A11 A10 DQ0 DQ1 DQ2 DQ3 W
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 E VSS
24 23 22 21 20 19 18 17 16 15 14 13
BLOCK DIAGRAM
A A A A A A A A ROW DECODER MEMORY MATRIX 256 ROWS x 256 x 4 COLUMNS
DQ0 * * * DQ3 A A A * * * INPUT DATA CONTROL
COLUMN I/O COLUMN DECODER
* * *
PIN NAMES
A0 - A15 . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . Chip Enable DQ0 - DQ3 . . . . . . . Data Input/Output VCC . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . No Connection
A
A
A
A
A
E W
REV 5 5/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MCM6708A 2-1
TRUTH TABLE (X = Don't Care)
E H L L L G X H L X W X H H L Mode Not Selected Read Read Write Output High-Z High-Z Dout Din Cycle -- -- Read Cycle Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature -- Plastic Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 2.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH Min 4.5 2.2 Typ 5.0 -- -- Max 5.5 VCC + 0.3* 0.8 Unit V V V
VIL - 0.5** * VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 2.0 ns) or I 30.0 mA. ** VIL (min) = - 0.5 V dc @ 30.0 mA; VIL (min) = - 2.0 V ac (pulse width 2.0 ns) or I 30.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH, Vout = 0 to VCC) Output High Voltage (IOH = - 4.0 mA) Output Low Voltage (IOL = 8.0 mA) Symbol Ilkg(I) Ilkg(O) VOH VOL Min -- -- 2.4 -- Max 1.0 1.0 -- 0.4 Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Active Supply Current (Iout = 0 mA, VCC = max, f = fmax) AC Standby Current (E = VIH, VCC = max, f = fmax) CMOS Standby Current (VCC = max, f = 0 MHz, E VCC - 0.2 V, Vin VSS, or VCC - 0.2 V) Symbol ICCA ISB1 ISB2 MCM6708A-8 185 120 50 MCM6708A-10 175 110 50 MCM6708A-12 165 105 50 Unit mA mA mA Notes 1, 2, 3 1, 2, 3
NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (MSB). 3. Data states are all zero.
MCM6708A 2-2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Address Input Capacitance Control Pin Input Capacitance (E, G, W) Input/Output Capacitance Symbol Cin Cin CI/O Max 5 5 6 Unit pF pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLES 1 AND 2 (See Notes 1 and 2)
MCM6708A-8 Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable Low to Output Active Chip Enable High to Output High-Z Symbol tAVAV tAVQV tELQV tAXQX tELQX tEHQZ Min 8 -- -- 3 1 0 Max -- 8 8 -- -- 4.5 MCM6708A-10 Min 10 -- -- 3 1 0 Max -- 10 10 -- -- 5 MCM6708A-12 Min 12 -- -- 3 1 0 Max -- 12 12 -- -- 6 Unit ns ns ns ns ns ns 4, 5, 6 4, 5, 6 Notes 3
NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max is less than tELQX min for a given device and from device to device. 5. Transition is measured 200 mV from steady-state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested.
AC TEST LOADS
+5 V OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF 480
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM6708A 2-3
READ CYCLE 1 (See Note)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV NOTE: Device is continuously selected (E = VIL, G = VIL). DATA VALID
READ CYCLE 2 (See Note)
tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX Q (DATA OUT) tAVQV NOTE: Addresses valid prior to or coincident with E going low. DATA VALID tEHQZ
MCM6708A 2-4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6708A-8 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 8 0 8 8 4 0 0 3 0 Max -- -- -- -- -- -- 4 -- -- MCM6708A-10 Min 10 0 9 9 5 0 0 3 0 Max -- -- -- -- -- -- 5 -- -- MCM6708A-12 Min 12 0 10 10 6 0 0 3 0 Max -- -- -- -- -- -- 6 -- -- Unit ns ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady state voltage with load of Figure 1B. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MOTOROLA FAST SRAM
MCM6708A 2-5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6708A-8 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Chip Enable to End of Write Data Valid to End of Write Data Hold Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tDVEH tEHDX Min 8 0 8 7 4 0 Max -- -- -- -- -- -- MCM6708A-10 Min 10 0 9 8 5 0 Max -- -- -- -- -- -- MCM6708A-12 Min 12 0 10 9 6 0 Max -- -- -- -- -- -- Unit ns ns ns ns ns ns 4, 5 Notes 3
Write Recovery Time tEHAX 0 -- 0 -- 0 -- ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX Q (DATA OUT) HIGH-Z tELWH tEHAX
MCM6708A 2-6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
J PACKAGE 300 MIL SOJ CASE 810A-02
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIMENSION R TO BE DETERMINED AT DATUM -T-. M
F
24 13
N
DETAIL Z D 24 PL 0.18 (0.007)
1
12
TA
S
-AL G
H BRK P -BM E 0.10 (0.004) C 0.18 (0.007)
S
T
B
S
M
K
DETAIL Z
-T-
SEATING PLANE
R 0.25 (0.010)
S
S RAD TB
S
DIM A B C D E F G H K L M N P R S
INCHES MIN MAX 0.620 0.630 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC -- 0.020 0.035 0.045 0.025 BSC 0_ 5_ 0.030 0.045 0.335 0.345 0.260 0.280 0.030 0.040
MILLIMETERS MIN MAX 15.75 16.00 7.50 7.74 3.26 3.75 0.39 0.50 2.24 2.48 0.67 0.81 1.27 BSC -- 0.50 0.89 1.14 0.64 BSC 0_ 5_ 0.76 1.14 8.51 8.76 6.61 7.11 0.77 1.01
M
MOTOROLA FAST SRAM
MCM6708A 2-7
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
6708A
X
XX
XX
Shipping Method (R2 = Tape and Reel, Blank = Rails) Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns) Package (J = 300 mil SOJ)
Full Part Numbers -- MCM6708AJ8 MCM6708AJ10 MCM6708AJ12
MCM6708AJ8R2 MCM6708AJ10R2 MCM6708AJ12R2
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MCM6708A 2-8
*MCM6708A/D*
MCM6708A/D MOTOROLA FAST SRAM

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